The invention relates to a method for producing ferroelectric strontium bismuth tantalate (SBT), to a method for fabricating a ferroelectric storage capacitor which includes a ferroelectric SBT layer of this type, to a semiconductor memory which includes the storage capacitor, and to a method for fabricating a semiconductor transistor which includes a ferroelectric SBT layer. In the strontium bismuth tantalate material, the tantalum content can be at least partially replaced by the element niobium.
In the semiconductor industry, in particular the silicon industry, it is now known to use ferroelectric or paraelectric materials for various purposes. Layers of this type can be used as replacements for the dielectric, which normally consists of an oxide or nitride layer, of a storage capacitor of a DRAM (Dynamic Random Access Memory) semiconductor memory. The advantage of these xe2x80x9cFeRAMsxe2x80x9d is: first the much higher dielectric constant of the ferroelectric material, and second the possibility of fabricating a nonvolatile memory module by the remanent polarization of the ferroelectric material.
Furthermore, in the case of MOS transistors, a ferroelectric layer can be formed as a replacement for the gate oxide layer as an insulating layer between the gate electrode and the channel section of the semiconductor surface, with the result that a nonvolatile memory transistor can be fabricated.
Strontium bismuth tantalate, with a composition SrBi2Ta2O9 (SBT) or SrBi2(Ta, Nb)2O9 (SBTN) has been known for some time as a ferroelectric material and can be deposited on a substrate, for example, by using a metal organic deposition process (MOCVD, MOD). However, the SBT/SBTN is generally not deposited in the ferroelectric phase, but rather is only converted into the ferroelectric phase by a subsequent heat treatment, known as the ferro-anneal, in an oxygen-containing atmosphere. The temperatures required for this heat treatment step according to the methods that have been disclosed hitherto are above 700xc2x0 C. For this reason, inert electrode materials, such as for example, platinum metals and conductive oxides thereof, have to be used to fabricate storage capacitors from this ferroelectric material.
To build up a DRAM memory cell, there are substantially two different structural concepts. A common feature of the two different structural concepts is that the switching transistor is formed in a lower level directly on the semiconductor substrate and the storage capacitor is arranged in a higher level. The switching transistor and the storage capacitor are separated from one another by an insulation layer that is positioned between them. According to a first structural concept (stacked cell), the switching transistor and the storage capacitor are arranged substantially directly above one another, and the lower electrode of the storage capacitor is electrically connected to the drain region of the MOS transistor by a contact hole (plug) which has been formed in the insulation layer and filled with a conductive material. According to a second structural concept (offset cell), the switching transistor and the storage capacitor are arranged offset with respect to one another, and the upper electrode of the storage capacitor is electrically connected to the drain region of the MOS transistor through two contact holes.
On account of the considerably smaller amount of space required by the xe2x80x9cstacked cellxe2x80x9d concept, this would under normal circumstances have to be preferred to the xe2x80x9coffset cellxe2x80x9d concept. However, the difficulty of the former concept is the need to arrange a diffusion barrier between the contact hole that has been filled with polycrystalline silicon or tungsten and the lower electrode, which usually consists of platinum, of the storage capacitor.
FIG. 1 shows a DRAM memory cell which uses the xe2x80x9cstacked cellxe2x80x9d concept. First of all, a MOS transistor 10 is fabricated on a semiconductor substrate 1 by forming a drain region 11 and a source region 12 by doping. A channel 13 is located between them. The conductivity of this channel can be controlled by a gate 14, which is arranged above the channel 13. The gate 14 may be formed by or connected to a word line of the memory component. The source region 12 is connected to a bit line of the memory component. The MOS transistor 10 is then covered with a planarization insulation layer 15, usually of an oxide such as SiO2. A storage capacitor 20, which substantially includes a lower electrode layer 21, a ferroelectric layer 22 and an upper electrode layer 23, is formed on this insulation layer 15. The lower electrode layer 21 is arranged above a contact hole 30, which is filled with a conductive material, such as polycrystalline silicon, and is connected to the drain region 11 of the switching transistor 10 by this contact hole. Between the lower electrode layer 21 and the contact hole 30 there is a diffusion barrier layer 25, which on the one hand prevents Si material from diffusing out of the contact hole 30 into the ferroelectric layer 22 and on the other hand prevents Bi/Bi2O3 and oxygen from diffusing out of the ferroelectric layer 22 into the contact hole 30. In particular the latter phenomenon may cause partial oxidation of the silicon of the contact hole 30, so that a nonconductive SiO2 layer is formed. Since the lower electrode layer 21 usually consists of platinum, which has a columnar grain structure, this platinum layer forms only an inadequate barrier to these diffusion phenomena.
Diffusion barriers are often formed from titanium layers or Ti/TiN double layers. However, it is known that these are unable to withstand a process temperature above 700xc2x0 C., as required in conventional methods for producing the ferroelectric layer 22. Hitherto, there has been no technologically established diffusion barriers which are suitable for such high process temperatures.
It is accordingly an object of the invention to provide a method for producing ferroelectric strontium bismuth tantalate which overcomes the above-mentioned disadvantages of the prior art methods of this general type.
In particular, it is an object of the present invention to provide a method for producing ferroelectric strontium bismuth tantalite, which can be integrated in a process for fabricating a component, such as a storage capacitor, and does not cause damage to other existing materials. In particular, it is also an object of the present invention to provide a method of this type in which the heat treatment step can be carried out at a lower temperature than that used in the prior art.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for producing ferroelectric SrxBiyTa2O9 (SBT) or SrxBiy(Ta, Nb)2O9 (SBTN). The method includes steps of: depositing SrxBiyTa2O9 (SBT) or SrxBiy(Ta, Nb)2O9 (SBTN) on a substrate, where 0.7xe2x89xa6xxe2x89xa61 and 2.1xe2x89xa6yxe2x89xa63.0; and performing a heat treatment step at a temperature T1 being less than 700xc2x0 C., until the SrxBiyTa2O9 (SBT) or the SrxBiy(Ta, Nb)2O9 (SBTN) has adopted a ferroelectric phase.
In accordance with an added feature of the invention, after performing the heat treatment step, which defines a first heat treatment step, performing a second heat treatment step at a temperature T2, where 550xc2x0 C.xe2x89xa6T2xe2x89xa6700xc2x0 C.; and simultaneously with performing the second heat treatment step, removing bismuth that evaporates from the SrxBiyTa2O9 (SBT) or the SrxBiy(Ta, Nb)2O9 (SBTN) during the second heat treatment step by pumping out the bismith.
In accordance with an additional feature of the invention, when performing the step of depositing the SrxBiyTa2O9 (SBT) or the SrxBiy(Ta, Nb)2O9 (SBTN) on the substrate, insuring that yxe2x89xa72.4; and when performing the heat treatment step, insuring that T1xe2x89xa6660xc2x0 C.
In accordance with another feature of the invention, the method includes insuring that x lies in a range from 0.7xe2x89xa6xxe2x89xa60.9.
In accordance with a further feature of the invention, the method includes insuring that x=0.85.
A significant idea of the inventive method consists in depositing the SBT or SBTN material in a nonstochiometric composition, and in particular modifying the nominal composition SrBi2Ta2O9 or SrBi2(Ta, Nb)2O9 in such a manner that the element bismuth is deposited in a higher amount y. If in particular the strontium content is denoted by x and the bismuth content is denoted by y, the ranges 0.7xe2x89xa6xxe2x89xa61.0 and 2.1xe2x89xa6yxe2x89xa63.0 are provided for the variables x, y. With these content ranges, it is possible, in a subsequent method step, to carry out a heat treatment at a temperature T1 which is lower than 700xc2x0 C. and in this way to convert the SBT/SBTN material into a ferroelectric phase.
As the bismuth content y increases, the temperature T1 of the heat treatment step required to convert the material into the ferroelectric phase falls. In particular, for a bismuth content yxe2x89xa72.4, it is possible to use a temperature T1xe2x89xa6660xc2x0 C.
If appropriate, excess bismuth should be expelled from the SBT/SBTN layer by using a second heat treatment step after the ferroelectric phase has been produced. This second heat treatment step can be carried out at a temperature T2 of 550xc2x0 C. xe2x89xa6T2xe2x89xa6700xc2x0 C. The bismuth that has been expelled from the ferroelectric material is concurrently removed by being pumped out. Bismuth escapes either in its elemental form or as the molecule Bi2O3. The high vapor pressure of the bismuth in SBT leads to a partial pressure in the surrounding atmosphere. If the vaporized Bi atoms or molecules are continuously removed from the gas phase, the excess Bi in the layer can be effectively reduced. This can be achieved either by lowering the overall pressure, by increasing the process gas flowrate and/or by using a longer conditioning time. The process gases used may be O2, N2, Ar or He, and the pressure preferably lies below 100 torr.
The inventive method also makes it possible to set the strontium content to be lower than 1, since Sr-deficient SBT increases the remanent polarization of the ferroelectric material. The Sr content x can therefore advantageously be set in a range between 0.7 and 0.9, preferably 0.85.
Therefore, with the inventive method, it is possible to incorporate the production of a ferroelectric layer in a compatible way in an overall process for fabricating a complex component. In particular, it is possible to fabricate a ferroelectric storage capacitor by first of all depositing a first electrode layer on a substrate, then producing a ferroelectric SBT or SBTN layer on the first electrode layer using the inventive method and finally to deposit a second electrode layer on the ferroelectric layer. The electrode layers may be produced from a platinum metal, in particular platinum, or an oxide of a platinum metal or another conductive oxide. If appropriate, the electrode layers can also be produced from a conventional electrically conductive material at a sufficiently low temperature T1 of the heat treatment step.
The invention also relates to a method for fabricating a semiconductor memory, in which first of all a switching transistor is formed on a semiconductor substrate, then an insulation layer is applied to the switching transistor, and finally, as described above, a ferroelectric storage capacitor is fabricated on the insulation layer, in such a manner that one of the electrode layers of the storage capacitor is connected to the source region or the drain region of the switching transistor. To fabricate a semiconductor memory in accordance with the xe2x80x9cstacked cellxe2x80x9d concept, it is possible for a diffusion barrier layer to be introduced between the first electrode layer of the storage capacitor and the insulation layer.
The invention also relates to a method for fabricating a semiconductor transistor, in which first of all source and drain regions are formed in a semiconductor surface on either side of a channel region. Then a ferroelectric SBT or SBTN layer is produced on the semiconductor surface above the channel region using the inventive method for doing so described above, and finally a gate electrode layer is applied to the ferroelectric layer. In addition, a CeO2 or ZrO2 interlayer may be applied to the semiconductor surface above the channel region prior to the production of the ferroelectric layer, and the ferroelectric layer can then be produced on this interlayer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for the low-temperature processing of a ferroelectric strontium bismuth tantalate layer, and methods for the fabrication of ferroelectric components using the layer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.